1. Field of the Invention
The present invention relates to a driving circuit capable of enhancing response speed and related method, and more particularly, to a driving circuit and related method that dynamically increases an input stage bias current of an operational amplifier for enhancing response speed of the operational amplifier according to a voltage difference between an input voltage and output voltage of the operational amplifier.
2. Description of the Prior Art
An operational amplifier is a widely used element for realizing a variety of circuit functions. Taking driving circuits of a liquid crystal display (LCD) for example, the operational amplifier can be used as an output buffer, which charges or discharges loading ends, i.e. liquid crystals, according to analog signals outputted by a front stage digital to analog converter (DAC), for driving corresponding pixel units on the LCD. However, with increases in size and resolution of the LCD, data quantity processed by the driving circuits per unit of time is also increasing significantly, so that response speed of the operational amplifier, also called slew rate, has to be enhanced as well.
In a conventional driver chip, the operational amplifier generally has a two-stage structure, which includes a first stage amplification circuit (input stage) and a second stage output circuit (output stage). The first stage amplification circuit is utilized for increasing current or voltage gain of the operational amplifier, while the second stage output circuit is utilized for driving capacitive or resistive loads connected to the operational amplifier. In addition, since the operational amplifier may suffer loop instability problems, Miller compensation capacitors are commonly implemented to perform frequency compensation for improving loop stability.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional operational amplifier 100. The operational amplifier 100 is a rail-to-rail operational amplifier and includes an input stage 110 and an output stage 120. The input stage 110 includes an N-type differential pair 112 and a P-type differential pair 114. The N-type differential pair 112 is formed by matched NMOS transistors MN1, MN2 and a bias transistor MN3. The bias transistor MN3 is coupled to source electrodes of the NMOS transistors MN1, MN2, and is utilized for providing a fixed static current (or driving current) to the N-type differential pair 112. Similarly, the P-type differential pair 114 is formed by matched PMOS transistors MP1, MP2 and a bias transistor MP3. The bias transistor MN3 is coupled to source electrodes of the PMOS transistors MP1, MP2, and is utilized for providing a fixed driving current to the P-type differential pair 114. In addition, the input stage 110 further includes a first current mirror 130, a second current mirror 140 and a third current mirror 150. The first current mirror 130 and the second current mirror 140 are indicated by current source symbols IP5, IP6 and current source symbols IN5, IN6, and utilized as active loads of the N-type differential pair 112 and the P-type differential pair 114, respectively. The third current mirror 150 is indicated by current source symbols 17, 18, and is utilized for summing up signals of the N-type differential pair 112 and the P-type differential pair 114 to output to the output stage 120.
The output stage circuit 120 is a class AB push-pull output circuit formed by transistors MP9 and MN9, in which an output terminal AVO of the output stage circuit 120 is coupled to an input terminal AVN of the input stage 110 for forming an output buffer with unit gain and negative feedback configuration. In addition, the operational amplifier 100 further includes compensation capacitors CM1 and CM2, placed between the input stage 110 and the output stage circuit 120, for performing pole-splitting for output signals of the input stage 110 and the output stage 120, so as to enhance loop stability. Detailed operation of the operational amplifier 100 is well-known by those skilled in the art, and not narrated herein.
Generally, the response speed of the operational amplifier 100 is decided by the bias currents of the input stage and the output stage. However, in order to drive external loads of the operational amplifier 100, the output stage driving current is generally greater than the input stage bias current. In this situation, the response speed of the operational amplifier 100 may be restricted by, or depend on, how fast the input stage bias current charges or discharges the compensation capacitors CM1, CM2, and can be expressed by the following slew rate equation:
      SR    =                  I        C            =                        Δ          ⁢                                          ⁢          V                t              ,in which “I” indicates a bias current provided by the transistor MN3 or MP3, “C” indicates capacitance of the compensation capacitors CM1 or CM2, and “ΔV” indicates voltage variation of the output terminal AVO. Thus, it can be seen that when the bias current of the input stage 110 is increased, the compensation capacitors can be charged or discharged much faster, so the response speed of the operational amplifier 100 can be enhanced as well.
Thus, in the prior art, the internal slew rate of the operational amplifier is generally enhanced by increasing the bias current of the input stage circuit. However, this not only increases circuit area, e.g. by increasing layout area of the bias transistors, but also causes additional power consumption of the operational amplifier.